FPGA + Verilog

Board Details :

PICO Computing E-101 

• (E101_Quick_Ref.pdf) 

• Spartan 6 data sheets here 

• "Data Sheet" here (crap) 

• Chip Data Sheet here 

• std_logic values 

Good for cryptography/cryptanalysis, huh? ... huuuuuh..... Zodiac killer project application... ?!? :D

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Using "VHDL: Learn By Example" to Understand VHDL:

Entity ENT_NAME is
port(    VAR1: in std_logic;
            VAR2: out std_logic_vector(7 downto 0);
             ...
             VARN: in std_logic               <--------------NO ";" for last entry
);
end ENT_NAME;
architecture ARCH_NAME of ENT_NAME is
    component OTH_ENT_NAME is
    port(    A:   in std_logic;
                ...
                B:   in std_logic                     <-------------------NO ;
     );
     end component;
    signal SIG_NAME: std_logic;
    ...
begin
    process( INP_VARS....)
    begin
    [LOGIC GOES HERE];
    end process;
    GATE_NAME: ENT_NAME port map (COMP_VARS=>ENT_VARS);
end ARCH_NAME; 

VHDL QUESTION:     Q: When is a process necessary? For multi-line logic only? For dependencies or certain operations?
     A: Processes are required to reuse code. (Change in parameter values triggers re-run).

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Verilog

Using "Verilog: Learn By Example"

Blocking vs. Non-Blocking assignments  

+ = Blocks procedural flow (Assignment happens first. Rest blocked)        

+ Use for time sensitive     

+ <= Doesn't         + Can be executed w/o dependency/timing issues        + Several register assignments in same time step        + Resembles actual hardware more Verilog QUESTIONS:     Q: When is it necessary to list "@ always" parameters with "or" vs. a comma?

BLOGGER IS MESSING UP MY FREAKING FORMATTING. ^ GAAAAH
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Driver Issues:

Install Digilent Adept System (at least v2.4)Install Plugin (follow pdf directions)answers here maybe? http://www.xilinx.com/support/answers/30184.htmDocumentation we were following for  DRIVERS http://www.xilinx.com/support/documentation/user_guides/ug344.pdf

NOPE^

I HATE DRIVERS.


But not really.


Please work.


I'm soorrrrryjustworkplzstopthetortuuuureee....


*********USE THIS DRIVER - PICK 64 BIT EVEN IF ON 32 BIT ****************


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Immediate Goal: Run and understand this example.
- Helpful when adding pins...kinda...notreally....
- Testbench related here




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Misc Resources:

TestBench TutorialVerilog 

TutorialVerilog Workflow (Work flow, colorful tutorial)

Misc:

WANT (to make) --> Noisy Jelly 

Understanding RSA